ATMP = the process
The set of back-end steps (assembly, test, marking, packaging) performed on a wafer. It describes what is done.
Assembly, Test, Marking & Packaging — the hands-on back-end work that turns a finished wafer into a usable chip.
The back-end flow
Outsourced Semiconductor Assembly & Test — a specialist firm that performs ATMP for chipmakers, on contract.
Who does the work
a third-party provider, on contract
OSAT stands for Outsourced Semiconductor Assembly and Test. An OSAT is a company that takes finished silicon wafers from a fab and turns them into packaged, tested chips ready to be soldered onto a board — on contract, for chipmakers who don't do that step themselves. Think of it as the specialist back end of the supply chain: fabs make the wafers, OSATs assemble, package and test them.
ATMP stands for Assembly, Test, Marking and Packaging — the back-end process that converts a completed wafer into a usable chip. It covers cutting the wafer into individual dies, mounting and wiring each die, encapsulating it, marking it, and testing that it works. In India's policy language (the India Semiconductor Mission), “ATMP” is the term used for this stage, and it's where most of the approved factory build-out is concentrated.
They're closely related and often used interchangeably, but they answer different questions.
The set of back-end steps (assembly, test, marking, packaging) performed on a wafer. It describes what is done.
A third-party provider that performs ATMP for other companies. It describes who does it — an outsourced specialist rather than the chip designer in-house.
In short: every OSAT does ATMP, but not all ATMP happens at an OSAT (some chipmakers run their own in-house assembly & test). For skilling and hiring, the hands-on capability is the same.
From a finished wafer to a tested, packaged chip.
The wafer is cut into hundreds of individual dies (the bare chips).
Each die is precisely mounted onto a leadframe or substrate.
Ultra-fine wires connect the die's pads to the package's leads.
The die and wires are encapsulated in protective compound.
The package is laser-marked, then leads are trimmed and bent to shape.
Electrical test and quality inspection confirm each chip works before shipping.
The “package” is the body that protects the die and connects it to the outside world.
Quad Flat No-lead — a compact, leadless package, very common in modern electronics.
Small-Outline ICs and other leaded packages — the classic gull-wing chips.
Ball Grid Array — connections via a grid of solder balls under the package, for high pin counts.
The die is flipped and bonded directly, removing wire bonds for speed and density.
Packaging done while still on the wafer, for the smallest possible footprint.
Stacking and integrating multiple dies — the fast-growing frontier of packaging.
India's approved semiconductor projects are weighted heavily toward assembly, test & packaging — the first units (Micron at Sanand; the CG Power–Renesas–Stars OSAT line) are an ATMP/OSAT build-out, and they recruit locally. Chip design talent is comparatively well-served in India; the binding constraint is hands-on manufacturing-floor skill. That's the gap — and the opportunity.
Outsourced Semiconductor Assembly and Test.
Assembly, Test, Marking and Packaging.
Packaging is one part of it. OSAT covers assembly and test as well as packaging — the whole back end, done on contract.
Yes — ATMP is the common name in India for the back-end stage that turns a finished wafer into a packaged, tested chip.
We advise institutions on real, plant-linked assembly, test & packaging programmes.