Every term you’ve seen but never had explained clearly Semiconductor Terms Explained
OSAT. ATMP. Fabless. IDM. 28nm. Tape-out. SiC. Advanced packaging. Plain English, with Indian examples, for students, engineers and anyone navigating India’s chip build-out.
The complete glossary
Filter by category or search by keyword. Each term includes what it means, why it matters for India, and a real Indian example where one exists.
A company that takes finished wafers from a fab and packages, assembles and tests them into working chips — on contract for chip designers and IDMs who outsource that step. The “outsourced” is the key word: the chip designer sends wafers, the OSAT sends back finished parts.
The four back-end steps that convert a finished wafer into a usable chip: (1) Assembly — dicing the wafer and bonding dies to packages; (2) Test — checking every chip works electrically; (3) Marking — laser-printing the part number; (4) Packaging — protecting the die in its final housing. OSAT companies run ATMP processes; so do IDMs doing it in-house.
A company that designs semiconductor chips but owns no manufacturing facility. It sends designs to a foundry (like TSMC) which fabricates the wafers, then to an OSAT which packages and tests them. This model concentrates a company’s resources on design IP rather than capital-intensive manufacturing.
A company that designs AND manufactures its own chips in-house, rather than outsourcing either step. IDMs own fabs (for fabrication) and often run their own back-end (ATMP) as well. Intel, Samsung and Texas Instruments are global examples. Rare because of the enormous capital required for both activities.
A factory that manufactures wafers for other companies’ chip designs, without designing chips itself. TSMC (Taiwan) is the world’s largest foundry and makes chips for Apple, NVIDIA, AMD and hundreds of others. The “pure-play” means the foundry has no competing chip-design business of its own.
Roughly the size of the smallest features on a chip, in nanometres. Smaller = more transistors packed per unit area = faster, more power-efficient, costlier to manufacture. 180nm (what SCL Mohali runs) is mature and reliable — ideal for space, defence and power devices. 28nm (Tata-PSMC Dholera target) is mature-advanced — used for automotive, industrial, IoT. 5nm (TSMC, Samsung) is cutting-edge — flagship smartphones, AI chips, GPU cores.
Modern packaging formats that go beyond one chip in one package: Fan-Out Wafer Level Packaging (FOWLP) embeds the die in a reconstituted wafer for ultra-compact footprints. 2.5D places multiple dies side-by-side on a silicon interposer. 3D stacking puts dies vertically on top of each other. Chiplets break a big chip into smaller functional blocks connected at close range. These approaches push performance beyond what process node scaling alone can deliver.
The most common method of connecting a silicon die to its package: ultra-fine gold or copper wires (thinner than a human hair) are bonded between the contact pads on the die and the leadframe or substrate. Done by automated wire bonders. The wire bond engineer owns this process and monitors for failures like non-sticking bonds, wire sweep and bond lift.
Instead of wiring the top of the die to a package, the die is flipped face-down and bonded directly via an array of tiny solder bumps on its surface. No wires means higher performance (shorter electrical paths), better heat dissipation, and higher connection density. Used in high-performance chips: CPUs, GPUs, smartphone SoCs.
The step in which the bare silicon die is placed and bonded onto the package substrate or leadframe, typically using conductive epoxy, solder or sintered silver paste. Die-tilt, voids in the adhesive and cure-profile control all affect thermal and electrical performance. One of the first process steps after wafer dicing.
ATE is the hardware and software system that tests packaged chips electrically before they ship. Parametric test checks that voltage, current and timing parameters meet specification. Functional test verifies the chip actually does what it is designed to do. Test engineering is a dedicated discipline — one of the highest-demand roles at Indian OSAT facilities because India has almost no trained ATE engineers domestically.
The software tools used to design semiconductor chips. Without EDA, designing the billions of transistors in a modern chip would be impossible. Major EDA vendors: Synopsys, Cadence, Siemens EDA (formerly Mentor). EDA tools cover every stage from logic design and simulation to physical layout and sign-off.
The dominant transistor technology used in virtually all digital chips today. CMOS uses pairs of complementary transistors (PMOS and NMOS) that consume very little power when not switching. It is the technology behind microprocessors, memory, and most logic devices. SCL Mohali operates a CMOS fab at 180nm.
The design of integrated circuits containing hundreds of thousands to billions of transistors on a single chip. “VLSI design” as a job description usually means chip design using EDA tools — RTL coding, verification, timing closure, physical layout. India has a large, well-established VLSI design industry in Bengaluru, Hyderabad and Pune.
The final milestone in chip design: the completed chip layout (a GDS file) is sent to the foundry for mask making and wafer fabrication. Named for the old practice of writing the data to magnetic tape. A tape-out is expensive (masks can cost millions of dollars) and takes months to return silicon. “First silicon” is what you get back.
A wide-bandgap semiconductor material that handles high voltages, high temperatures and high switching frequencies far better than conventional silicon. Essential for EV powertrains (inverters, on-board chargers), industrial motor drives, solar inverters, and fast-charging stations. SiC devices are bulkier and more expensive to make than silicon, but their efficiency advantages in high-power applications justify the cost.
DRAM (Dynamic Random Access Memory): fast, volatile working memory in your phone/PC — data disappears when power is off. NAND Flash: non-volatile storage used in SSDs, USB drives, smartphones — data persists. Logic: processing chips (CPUs, GPUs, microcontrollers, SoCs) that execute instructions. Different manufacturing processes, different applications, different market dynamics.
Front-end: wafer fabrication — building transistors and circuits onto silicon wafers using photolithography, deposition and etching. Requires a fab. Capital-intensive; measured in nanometre nodes. Back-end: ATMP — dicing the wafer into individual dies, then assembling, testing, marking and packaging them. Requires an OSAT or back-end facility. Equally technical, less capital-intensive, but just as critical.
A room with extreme particle and contamination control. In semiconductor manufacturing, a single dust particle can destroy a chip. ISO Class 5 (old “Class 100”) allows fewer than 100 particles ≥0.5µm per cubic foot. ISO Class 8 (“Class 100,000”) is less strict and used for less sensitive assembly steps. Working in a clean room requires full gowning: bunny suit, gloves, hood, face mask.
A thin, flat disc of crystalline silicon on which hundreds or thousands of chip circuits are simultaneously fabricated by the fab. Common sizes: 200mm (8-inch) — used by older/specialty fabs including SCL Mohali; 300mm (12-inch) — used by leading-edge and high-volume fabs, including the planned Tata-PSMC Dholera fab. Larger wafers yield more chips per pass and reduce cost per chip.
A wafer-level process that deposits solder bumps (tiny balls of metal alloy) on the contact pads of each die before dicing. These bumps become the connections when the die is flipped and bonded to the substrate in flip-chip assembly. Wafer bumping sits between front-end fab and back-end ATMP in the manufacturing flow.
An India Semiconductor Mission scheme that supports chip design companies financially: up to 50% of eligible design expenditure (capped at ₹15 crore/application) and 4–6% of net sales over 5 years (capped at ₹30 crore). Administered through C-DAC’s ChipIN Centre. Targets IC, chipset, SoC, system and IP core design. As of January 2026, 24 projects supported, 16 tape-outs completed, ₹430 crore in VC attracted.
An ISM academic programme that provides free EDA tools to Indian colleges and universities, and enables student-designed chips to be fabricated at SCL Mohali. Targets 85,000 trained semiconductor engineers over 10 years. ISM 2.0 expands the institutional base from 315 to 500 colleges. The scheme’s goal: create a chip-design talent pipeline in India that feeds both the domestic and global semiconductor industry.
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