Supply chain sovereignty
India’s defence, space, railway and telecom sectors depend on imported silicon. A domestic 28nm fab changes that risk profile. Chips for ISRO and DRDO applications no longer need to cross borders.
₹91,000 crore. 28nm–110nm. 300mm wafers. PSMC as technology partner. ASML equipment deal signed May 16, 2026. First silicon: late 2026.
India has produced semiconductor chips before — SCL Mohali has run a government R&D fab at 180nm since the 1980s. The Tata Electronics–PSMC facility under construction in Dholera is a different category entirely: the first commercial logic fab on Indian soil, designed to manufacture at process nodes the market actually needs.
The fab will operate at 28nm to 110nm — trailing-edge by global standards, but the right nodes for the products India’s growing electronics sector needs: microcontrollers, power management ICs, display drivers, automotive chips, and industrial processors. 28nm is the strategically correct entry point; advanced nodes (sub-5nm) require decades of ecosystem depth India does not yet have.
Taiwan-based PSMC specialises in mature-node logic and is among Taiwan’s largest foundries outside TSMC. The partnership gives Tata access to proven process recipes, equipment qualification protocols, and yield engineering capability — the parts of a fab that cannot be purchased off a shelf.
On May 16, 2026, Tata Electronics signed a framework agreement with ASML, the Dutch company that manufactures every EUV lithography machine on earth. ASML will supply semiconductor manufacturing equipment and technology for the Dholera fab.
Lithography is the process of printing circuit patterns onto silicon wafers — the heart of every chip fabrication step. ASML holds a near-total monopoly: 80%+ of the global lithography market, and 100% of EUV machines. No fab at 7nm or below can exist without ASML EUV equipment. At the 28nm–110nm nodes Dholera targets, ASML’s DUV (Deep Ultraviolet) systems are the standard tool of choice.
ASML also operates under strict Dutch and Wassenaar Arrangement export controls and cannot sell EUV machines to China. That constraint is actively reshaping where advanced semiconductor equipment ends up — and India, with no ASML export restrictions and a government actively courting investment, is an increasingly attractive long-term market. The Dholera partnership puts India on ASML’s strategic map for the next decade.
India’s current ATMP and OSAT investments — Micron, Kaynes, CG Semi, Tata TSAT — package imported wafers into finished chips. India captures value at the back end of the supply chain, not the front. Dholera changes that.
India’s defence, space, railway and telecom sectors depend on imported silicon. A domestic 28nm fab changes that risk profile. Chips for ISRO and DRDO applications no longer need to cross borders.
Wafer fabrication is the highest-margin stage of the semiconductor value chain. ATMP is downstream and lower-margin. Dholera moves India up the stack.
A credible fab anchors an entire supply chain — substrate suppliers, specialty chemicals, EDA usage, equipment service companies. Dholera creates the gravitational centre that makes a real cluster possible.
The existence of a domestic fab changes what engineering students study and what institutions need to teach — creating demand for process engineers, lithography specialists and yield engineers that currently have no domestic employer.
28nm is not cutting-edge. TSMC’s leading node is 2nm. But 28nm is where a large share of the world’s chips are manufactured for volume commercial use: automotive microcontrollers, industrial sensors, display drivers, power management ICs, IoT chips. The global 28nm–180nm segment is large, growing, and exactly where India’s electronics sector needs supply. Dholera is appropriately positioned, not behind the curve.
A 300mm logic fab employs a different workforce profile from ATMP operators or chip designers. C2S trains designers; ATMP programmes build back-end operators. Front-end fab talent requires a distinct curriculum and equipment that institutions in India largely do not yet have.
Managing lithography, etch, deposition, CMP, implant and diffusion steps
Maintaining and qualifying ASML scanners, etch chambers, CVD tools and metrology systems
Analysing defect data, identifying failure modes, driving yield improvement across the process flow
Managing the interaction between process steps across the full wafer fabrication flow
Running wafers through individual tool steps under strict SOPs in an ISO-class environment
Using KLA, Onto and Applied Materials inspection systems to measure and characterise layers
Tata Electronics in a JV with PSMC (Powerchip Semiconductor Manufacturing Corporation) of Taiwan. Tata Projects is the construction contractor. ASML signed an equipment supply agreement in May 2026.
28nm to 110nm — covering core automotive, display driver, microcontroller, power management, and industrial processor nodes. The range most relevant to India’s domestic electronics demand.
First silicon (initial process qualification wafers) is targeted for late 2026, per Union Minister Ashwini Vaishnaw’s confirmed timeline. Full commercial production at scale is targeted around 2028.
On May 16, 2026, Tata Electronics and ASML signed a framework agreement for DUV lithography equipment supply and technology support for the Dholera fab. ASML supplies the machines that print circuit patterns on silicon wafers.
SCL Mohali (est. 1984) is India’s oldest chip facility — a government R&D fab at 180nm. Tata Dholera will be India’s first commercial logic fab at 28nm–110nm with 300mm wafers at commercial volume.
~₹45,500 crore — 50% of the total ₹91,000 crore project cost — through the India Semiconductor Mission’s fiscal support mechanism. Tata Electronics funds the remaining 50%.
We advise institutions on hands-on semiconductor programmes aligned with India’s new fabs — ATMP, OSAT, and front-end process training.