Launched December 2021. ₹76,000 crore corpus. 13 approved projects. Three facilities operational. Here is what the mission is, what it funds, what it has actually built, and what is still missing.
India imports roughly $30 billion in semiconductor chips annually — many of them made on processes that India’s own Semiconductor Laboratory in Mohali once aspired to lead. Despite four decades of fitful attempts, India had no commercial chip manufacturing as of 2021. ISM is the most serious attempt to change that.
ISM is a co-funding programme administered through MeitY (Ministry of Electronics and Information Technology) via the India Semiconductor Mission, a specialised body under Digital India Corporation. Companies apply; ISM contributes up to 50% of project cost in the form of fiscal support (capital subsidy equivalent). The applicant funds the rest and commits to delivery milestones.
ISM covers three distinct categories, each with its own incentive structure.
Front-end wafer fabrication facilities (logic, memory, display). Fiscal support of up to 50% of total project cost. The most capital-intensive category: a 28nm fab costs ₹91,000 crore (Tata–PSMC, Dholera). Only one fab has been approved under ISM to date.
Assembly, test, marking and packaging facilities; OSAT providers; Silicon Carbide and compound semiconductor fabs; discrete device manufacturers. Up to 50% of capex. The bulk of approved projects fall here. Most new hiring will come from this category.
For chip design startups and companies: up to 50% of eligible design expenditure (capped at ₹15 crore per application), plus 4–6% of net sales over 5 years (capped at ₹30 crore). Nodal agency: C-DAC’s ChipIN Centre. Targets IC, chipset, SoC, system and IP core design.
C2S is ISM’s academic pipeline programme: free EDA tools deployed across Indian institutions, with student-designed chips fabricated at SCL Mohali. It is primarily a design-side programme, but the fab link gives it a manufacturing dimension no other country offers at this scale.
EDA tools provided: Synopsys, Cadence, Siemens, Renesas, Ansys, AMD. ISM 2.0 (Budget 2026-27) expands C2S from 315 to 500 institutions and adds emphasis on manufacturing and equipment skills alongside design.
ISM is real and it is working. It is also worth being clear about what it has not yet achieved.
The Tata–PSMC Dholera fab targets first silicon in late 2026 and full production around 2028. Until that happens, India remains entirely dependent on imports for wafers. The ATMP layer being built now packages chips made elsewhere — which is valuable and necessary, but it is not yet a complete semiconductor industry.
One important marker of progress: on May 16, 2026, Tata Electronics signed a framework agreement with ASML — the sole supplier of EUV lithography equipment globally — confirming equipment supply for the Dholera fab. Equipment relationships of this kind are not formed with projects ASML considers high-risk; the commitment signals that the fab’s technology roadmap is credible at the equipment level. Full breakdown of the Dholera fab and the ASML deal →
The facilities are approved and being built. The trained workforce to run them does not exist yet at scale. C2S trains designers; India needs ATMP operators, technicians, process engineers, and equipment engineers — profiles that require hands-on training on real equipment. That gap is ISM’s biggest execution risk.
Global advanced packaging (fan-out, 2.5D, 3D stacking, chiplets) is a $46 billion market growing at ~9.5% per year (Yole Group). India’s approved ATMP projects are weighted toward conventional packaging. Kaynes and CG Semi are building toward more advanced formats, but none of India’s facilities currently does leading-edge advanced packaging at volume.
A functioning semiconductor cluster needs substrate suppliers, leadframe manufacturers, EMC compound suppliers, precision tooling makers, specialty chemicals, and equipment service companies — none of which India has domestically at scale. Every ISM-approved facility currently imports these inputs. Building domestic supply chain depth is the decade-long second layer of this programme.
Budget 2026-27 launched ISM 2.0 with a ₹1,000 crore FY27 provision as part of a broader ₹8,000 crore outlay. The second phase explicitly adds what the first phase underweighted: semiconductor equipment, materials and chemicals, indigenous IP development, and manufacturing skills. C2S expands from 315 to 500 institutions with new manufacturing curriculum alongside design. The strategic shift acknowledges that co-funding fabs and ATMP plants is necessary but not sufficient — India also needs to build the upstream supply chain and the downstream workforce simultaneously.
How Fidus works in this ecosystemDecember 2021, under the Ministry of Electronics and Information Technology (MeitY). The total corpus is ₹76,000 crore (~$10 billion). ISM 2.0 was announced in Budget 2026-27 with a further ₹8,000 crore outlay.
Up to 50% of project cost for fabs and ATMP/OSAT facilities, and up to 50% of eligible design expenditure (capped at ₹15 crore) for chip design companies under the DLI scheme.
Yes, in a limited sense: SCL Mohali has produced chips at 180nm for decades. The new wave — Micron Sanand, Kaynes, CG Semi — packages imported wafers into finished chips (ATMP/OSAT). India’s first commercial logic fab (Tata–PSMC, Dholera) targets first silicon in late 2026.
Design Linked Incentive: financial support for chip design companies in India. Up to 50% of eligible design expenditure (capped ₹15 crore/application) plus 4–6% of net sales over 5 years (capped ₹30 crore). As of January 2026, 24 projects were supported and 16 tape-outs had been completed.
We advise institutions and industry on building the hands-on skilling programmes that ISM’s approved facilities need to operate at scale.
