C2S is India's primary programme for putting professional semiconductor design tools into the hands of students and faculty. Free access to Synopsys, Cadence, Siemens EDA, and more — for institutions that enrol. Here is what's covered, how to apply, and how C2S fits into the broader ISM talent strategy.
Free access to professional EDA (Electronic Design Automation) tools from Synopsys, Cadence, and Siemens — the same tools used by Intel, Qualcomm, and every major chip design company globally. VLSI-Lab setup support and curriculum integration. Faculty training through NITTTR. Access to NSDC's semiconductor design bootcamps for enrolled students.
C2S is a chip design programme — it does not cover semiconductor manufacturing, ATMP/OSAT, or hands-on packaging skills. It does not provide fabrication access (tape-outs must be funded separately). It does not guarantee placement in manufacturing facilities. Under ISM 2.0, a manufacturing curriculum is being added alongside design, but the core programme remains design-focused.
C2S gives enrolled institutions access to the full professional EDA toolchain — the same tools that power chip design at every major semiconductor company. These tools cost tens of thousands of dollars per licence commercially; under C2S they are free.
Applications go through MeitY and are processed via the NIELIT / CDAC coordination mechanism. The process typically takes 3–6 months from application to tool access. AICTE-affiliated engineering colleges with ECE departments are the primary beneficiaries, but all NAAC-accredited institutions can apply.
Fabless chip design companies — Qualcomm India, Nvidia India, MediaTek India, Intel Design Centres. System design roles at Tata Elxsi, L&T Technology, HCL. Semiconductor IP companies. The ~20% of global IC design talent that India already holds — C2S expands that further.
National support: ~315 institutions enrolled, 85,000 engineers targeted. These numbers are design roles. India's design ecosystem is well-served by C2S — this is where C2S adds most value.
OSAT/ATMP operators and technicians — the roles Micron Sanand, Kaynes, CG Semi, and Tata TSAT actually need right now. Wire bonding, die attach, encapsulation, electrical test, ATE (Automated Test Equipment) operation, cleanroom protocols. These are hands-on, equipment-dependent skills that no EDA tool teaches.
Under ISM 2.0, a manufacturing curriculum is being added to C2S. But the hands-on OSAT skills gap is the most acute talent shortage in India's semiconductor ecosystem today — and C2S alone does not fill it. Full guide to OSAT training programmes →
What is the Chips to Startup (C2S) programme?
C2S is a MeitY initiative that provides free professional EDA tools (Synopsys, Cadence, Siemens) to enrolled engineering institutions in India. It targets training 85,000 chip design engineers and building a domestic semiconductor design talent pipeline. Launched alongside ISM 1.0 in 2021.
How many institutions are enrolled in C2S?
315+ institutions as of 2025. Under ISM 2.0, the target expands to 500 institutions, and a manufacturing-focused curriculum is being added alongside the existing design programme.
Is C2S free for institutions?
Yes — EDA tool licences, training, and curriculum support are provided at no cost to enrolled institutions. The institution must provide the hardware infrastructure (workstations, servers, lab space) and commit to integrating C2S into its curriculum.
Which EDA tools does C2S provide?
Synopsys (Design Compiler, IC Compiler II, PrimeTime, VCS), Cadence (Virtuoso, Innovus, Spectre, Xcelium), Siemens (Calibre, Questa), plus MATLAB/Simulink and Keysight ADS for RF/analog design.
Can C2S help institutions prepare students for OSAT/ATMP jobs?
C2S prepares students for chip design roles — not manufacturing. OSAT/ATMP facilities (Micron Sanand, Kaynes, CG Semi) hire operators, process technicians, and equipment engineers — roles that require hands-on manufacturing training, not EDA skills. Under ISM 2.0, a manufacturing curriculum is being added to C2S, but institutions serious about ATMP placement need a separate programme. Guide to OSAT training →
Does C2S help with tape-outs?
C2S provides the design tools needed to prepare a tape-out. It does not fund tape-out fabrication costs. Students and faculty who complete a chip design and want to tape it out must access Multi-Project Wafer (MPW) runs through MOSIS, IMEC IC-Link, or foundry programmes separately. Some C2S institutions have done tape-outs through IIT Bombay's VLSI Design Centre.
C2S serves the design side. The manufacturing side — what Micron, Kaynes, CG Semi, and Tata TSAT need — requires a separate programme. We help institutions build both.
