The talent pyramid
has five tiers.
India is building four.
NITI Aayog’s ten-year semiconductor roadmap asks for a National Semiconductor Talent Pyramid — a workforce trained at every level, from fab-ready cleanroom technicians up to system-level solution architects. It is the clearest official statement yet that design capability alone will not staff India’s chip industry. Map the country’s actual programmes against that pyramid and four tiers have something under construction. The fifth — the base, the widest one, the one the operating plants are recruiting for right now — has no national programme at all.
India’s first ten-year semiconductor roadmap
On 29 May 2026, NITI Aayog’s Frontier Tech Hub released Future of India’s Semiconductor Industry, unveiled by Finance Minister Nirmala Sitharaman and Electronics & IT Minister Ashwini Vaishnaw, with NITI Aayog Vice Chairman Ashok Lahiri, Distinguished Fellow Debjani Ghosh, and ISM CEO Amitesh Kumar Sinha present. It is the most comprehensive government-authored assessment of India’s chip ecosystem published to date.
The headline ambition is a $120–150 billion semiconductor value chain by 2035, carrying 10–13% of the global market, with 100-plus advanced design IPs developed domestically. The strategy is deliberately not a wafer race: it is a More-than-Moore approach concentrating on mature logic nodes, advanced packaging and OSAT, and wide-bandgap compound semiconductors — the segments where India can plausibly build durable advantage rather than chase a twenty-year capital deficit from behind.
The framework is five pillars. Four of them are about capital, technology and diplomacy. One is about people.
Pioneering R&D
Frontier research and design IP, targeting 100+ advanced semiconductor IPs in AI, quantum and high-performance compute.
Policy & Investment
Long-horizon capital, and an autonomous National Semiconductor Nodal Agency with a full-stack incentive regime.
Production
Advanced packaging, mature and compound wafer fabrication, critical materials, with a focus on defence and aerospace.
People
A National Semiconductor Talent Pyramid — workforce capability at every level, from fab-ready cleanroom technicians to advanced system-level solution architects.
Partnerships
Outcome-driven alliances with the US, Japan and the EU; critical mineral supply chains; technology transfer.
Why that one phrase matters
“From fab-ready cleanroom technicians to advanced system-level solution architects” is a government think tank stating, in a document launched by two Union Ministers, that India’s semiconductor workforce problem runs the full height of the organisation chart — not just the graduate-engineer band that C2S and the DLI scheme address. Until this roadmap, that argument had to be made by inference. It is now citable.
The pyramid, populated
NITI Aayog named the tiers. It did not say who fills them. Below, each tier is mapped against the programmes that actually exist in India today — announced, funded, and in most cases already running.
No national programme. No published headcount. No scheme scoped for it.
Tier widths represent relative headcount demand, not funding. Programmes listed are those publicly announced as of August 2026. Tier 5 status reflects the absence of a national scheme producing operators and technicians at plant scale — individual ITIs and private providers run relevant courses, but none is mapped to semiconductor cleanroom practice or linked to an operating facility.
The pyramid is upside down
In any functioning manufacturing sector, the base is the widest part of the workforce and the cheapest to train. India has inverted it. The narrowest tier — system architects — has two international university MoUs. The design tier has 320 institutions and ₹thousands of crores of EDA tooling. The base has nothing.
This is not incompetence. It is the predictable outcome of how the mission was sequenced. ISM 1.0 needed to prove India could attract fabs and packaging plants, and design talent was the credential that made the pitch credible. That worked. Twelve units are approved, three are operating and now exporting. But the plants that resulted do not primarily employ chip designers.
Thousands, not dozens
Micron’s Sanand facility runs roughly five lakh square feet of cleanroom. CG Semi’s G2 line is scaling toward 5,000-plus jobs. Tata’s Jagiroad plant is designed for 48 million chips a day. These are operator-heavy facilities.
Hired within commuting distance
Sanand, Dholera, Jagiroad, Bhubaneswar, Mohali, Bhiwadi. Relocation economics do not work at technician salaries, so floor roles are filled locally. Three national campuses do not reach those catchments.
Hours, not credits
Gowning discipline, particle behaviour, ESD handling, recognising a bonder drifting out of spec. None of it is taught in software and none of it is certified by a degree. It requires a controlled environment and repetition.
Building the base tier
Semicon 2.0’s Pillar 6 carries a ₹1,000 crore provision for industry-led research and training centres. It is the only instrument in the current policy set that can fund the base of the pyramid, and its operational guidelines have not yet published. That gap — between an approved provision and an open scheme — is the window.
Cite the pyramid, not the shortage
Workforce shortage estimates are industry projections and a reviewer can discount them. The talent pyramid is NITI Aayog’s own framing in a roadmap launched by the Finance Minister. Position a proposal as building a named tier of a government framework rather than as responding to a market forecast.
Sign the industry MoU before the scheme opens
Every Pillar 6 arrangement announced so far has an industry counterparty attached. Lam with IISc. NAMTECH with Micron, CG Power, Kaynes and Tata. A training centre proposal without a named employer partner asks the mission to solve the hardest part for you.
Scope to the plant, not to the syllabus
Start from the job descriptions an operating facility is recruiting against, map those to NSQF levels, then design backwards. A curriculum written first and matched to employers later produces graduates the plants will not interview.
Secure hands-on hours
The base tier cannot be delivered in software. That means a cleanroom — a modest ISO Class 7 or 8 training environment, shared access to an industry facility, or a partnership with a public institution that already has one. In the north, SCL Mohali is a national training hub with a ₹4,500 crore modernisation underway that explicitly includes training capability.
Four tiers are funded.
The fifth is the opportunity.
We advise institutions on plant-linked ATMP/OSAT programmes — model, funding route, faculty, NSQF certification and placement linkage. Free 45-minute consultation around Semicon India 2026. 7 slots remaining.