ISM Revises C2S Numbers Upward: 320 Institutions, 70,000 Trained — Target Still 500
The Semicon 2.0 scheme page on ism.gov.in now states 320 universities training students on complex chip design using the latest EDA tools, with around 70,000 students already trained. The July 15 Cabinet release recorded 315 universities and roughly 68,000 students. Small revisions, but they matter for anyone quoting the figures in a proposal.
The C2S numbers have moved three times this year: Minister Vaishnaw cited 67,000 engineers trained across 315 universities against an 85,000 ten-year target in February 2026; the Cabinet press release of 15 July recorded 68,000 across 315; the current ISM scheme page states around 70,000 across 320.
ISM’s own scheme page is the most current and most authoritative of the three. Under Semicon 2.0 the institutional footprint expands toward 500, and the mandate now explicitly includes cleanroom operations, fab construction and other hands-on ecosystem training delivered with active industry engagement. Student designs continue to be fabricated and tested at the Semi-Conductor Laboratory in Mohali.
Two practical points. First, if you are drafting a Pillar 6 proposal or a board note, quote 320 and 70,000 and cite the ISM scheme page — a reviewer working from the same source will notice a stale figure, and it is the cheapest possible credibility loss. Second, the gap between 320 and the 500 target is 180 institutional slots, and the mandate attached to them is no longer design-only. That is the addressable opportunity, and it is finite.
The direction of travel in these revisions is also worth noting: the design side keeps expanding and keeps being counted. There is still no equivalent published figure for operators or technicians trained for ATMP and OSAT floors — because there is not yet a programme producing them at a scale worth counting.