Plain-English resources on India’s chip build-out — the companies building it, the jobs it creates, the mission funding it — ₹76,000 crore under ISM 1.0, ₹1,27,500 crore approved for ISM 2.0 in July 2026 — the vocabulary behind it, and the Mohali corridor at its oldest address. Built for institutions, students, engineers and industry partners entering this space.
From first principles to hyper-local. Read in any order; each stands alone.
What is OSAT? What is ATMP? Most Indian engineers can name them but can’t explain them. This is the plain-English breakdown: the full back-end flow from wafer to packaged chip, how package families work (QFN, BGA, flip-chip, advanced), what the OSAT vs ATMP distinction actually means, and why India’s build-out is concentrated here.
The complete map of who’s building India’s semiconductor back-end: Micron (DRAM/NAND, Sanand), CG Power–Renesas (OSAT, Sanand), Kaynes Semicon (multi-chip modules), Tata TSAT (48M chips/day, Assam), HCL–Foxconn (Jewar), CDIL (SiC, Mohali), SCL (government fab, Mohali), and more. Status, capacity, investment and hiring information for each.
What ATMP facilities actually hire for — eight manufacturing-floor roles in plain English (wire bond, die attach, flip chip, test, reliability, equipment, yield, package design). Salary ranges at every level. The design vs manufacturing distinction that matters for where you apply. What to search on Naukri and LinkedIn. Why early movers have a structural advantage.
The ₹76,000 crore ($10B) programme that drove India’s first chip build-out — and the ₹1,27,500 crore ISM 2.0 that the Cabinet approved on 15 July 2026. The three ISM 1.0 schemes (fab, ATMP/OSAT, DLI design), the six ISM 2.0 pillars, the project timeline from CG Semi G1 pilot (Aug 2025) onward, C2S skilling stats, DLI outcomes, and an honest assessment of what the mission has not yet achieved.
The honest split: chip design courses are widely available (C2S, 320 institutions, free EDA tools). Hands-on manufacturing courses in ATMP/OSAT are scarce, because they need real equipment and trained faculty. What an operator course actually covers, how NSQF certification works, what makes a programme plant-linked, and why placement is the proof point.
24 terms defined with Indian examples and live filter by category. OSAT, ATMP, fabless, IDM, foundry, process node (what 28nm actually means), wire bonding, flip chip, die attach, ATE, EDA, CMOS, VLSI, tape-out, SiC, DRAM, NAND, wafer, front-end vs back-end, C2S, DLI and more. Filterable by back-end, front-end, design, business model, India-specific, and materials.
India’s oldest chip address — SCL (1984, India’s only government fab, Mangalyaan chips, ₹4,500 crore upgrade announced Nov 2025) and CDIL (1964, India’s oldest semiconductor company, first SiC maker, ISM-approved expansion Aug 2025). The April 2026 NXP R&D courtship in the Netherlands. Punjab’s IBDP 2026 incentives (125% FCI, 15yr, ₹500cr cap). The institutional talent pipeline. A realistic 5-year outlook for the Mohali semiconductor corridor.
India’s first commercial logic fab is under construction in Dholera, Gujarat. ₹91,000 crore. 300mm wafers. 28nm–110nm process nodes on the roadmap. PSMC as technology partner. On May 16, 2026, Tata Electronics signed a framework agreement with ASML — the Dutch company that manufactures every EUV lithography machine on earth — confirming equipment supply for the fab. First production is now tracking to 90nm in mid-2028 rather than the 28nm/late-2026 target announced in 2024 — a commercial calibration toward the automotive, industrial and power nodes India actually consumes. This is still the project that turns India from a chip-packaging country into a chip-making country.
Odisha’s High-Level Clearance Authority approved Sancode Semi’s ₹1,650 crore OSAT unit in Khordha district on February 2, 2026. 570 direct jobs. What the approval means, what the facility will do, and what skills Odisha’s engineering institutions need to build for it.
The actual job titles Indian semiconductor companies are hiring for in 2026 — RTL Design, Verification, Physical Design, Process Engineer, ATMP Technician, Equipment Engineer and more — with real salary bands and the degree path that gets you there.
The government has now named the skills gap in policy. Cabinet approval on 15 July 2026 expanded the C2S mandate from 320 institutions toward 500, and added cleanroom operations, fab construction and OSAT manufacturing to what ISM funds — with ₹1,000 crore behind industry-led training centres. What Pillar 6 actually pays for, who qualifies, why an industry MoU is the binding requirement, and the four steps institutions should complete before September 17.
Semicon India is written for exhibitors and investors. If you run a college, polytechnic or ITI, almost none of the official programme is aimed at you — and yet these are the only three days of the year when ISM officials, plant HR heads, equipment vendors and six national delegations are in one building. Hour by hour: what to carry and what to leave at home, how to work the 360 sqm Workforce Development Pavilion, the six country pavilions read for talent rather than trade, and the fourteen-day follow-up window that decides whether any of it was worth it.
The Indo-Swiss Training Centre was inaugurated in Chandigarh in December 1963, built with the Swiss Foundation for Technical Assistance under what is now CSIR-CSIO. It trains precision engineers, not semiconductor engineers — and tolerance work, machine setup, process discipline and measurement are exactly what an OSAT floor hires for. Twenty kilometres from SCL Mohali, sixty years before the fabs arrived. Plus the four things BDUni names as the base-tier requirement: infrastructure, equipment, curriculum, certification.
NITI Aayog’s Future of India’s Semiconductor Industry roadmap, released 29 May 2026, calls for a talent pyramid spanning fab-ready cleanroom technicians to system-level solution architects. Mapped against India’s actual programmes — C2S, Lam and IISc, NAMTECH, Purdue and ASU — four tiers are under construction and the base is empty. Cite this framework in a Pillar 6 proposal rather than an industry shortage estimate: it is the government’s own language.
Workforce MoUs with Purdue University and Arizona State. A Lam Research partnership with IISc deploying the Semiverse virtual-fab platform nationally, targeting 60,000 fabrication engineers. NAMTECH’s first manufacturing cohort at IIT Gandhinagar with Micron, CG Power, Kaynes and Tata as partners. And private universities announcing semiconductor degrees with edtech partners. Four layers of response — research capability, process simulation, elite cohorts, degree products — and beneath all of them, the operator and technician layer the plants are hiring for in volume, which no announced programme is scoped to fill.
Vaishnaw posted the scoreboard on 2 August 2026: twelve approved semiconductor units, $20 billion committed, three already making chips. The progress is real — and the 2005 comparison it invites is fair. What the post doesn’t address is the supply chain behind those plants: lithography, deposition and metrology tools, photoresists, electronic-grade gases, wafer-grade silicon. ISM 2.0’s 30% machines-and-materials incentive is the first policy instrument aimed at that gap.
September 17–19, Yashobhoomi, New Delhi. Theme: “Silicon to Systems: Building the Ecosystem.” 600+ exhibiting companies from 52 countries across 18,000 sqm, six country pavilions (Japan, Korea, Netherlands, Singapore, Malaysia, Sweden), and a 360 sqm Workforce Development Pavilion. Co-located with electronica and productronica India. This is where ISM 2.0 implementation guidelines, first-tranche allocations and facility MoUs are all expected to land — which makes it the single most operationally useful three days of the year for institutions building semiconductor programmes.
If you want to know what semiconductor jobs exist, what they pay, what degree you need, and where the facilities are — the jobs guide and courses guide are your starting points. The glossary will fill the gaps when you encounter unfamiliar terms.
If you’re evaluating whether and how to add semiconductor skilling to your institution, the courses landscape and the ISM guide explain the policy environment and what funding is available. The ISM 2.0 Pillar 6 analysis covers what the training centre scheme funds and what to prepare before Semicon India. The talent enablement page is how Fidus can help directly.
If you need a clear, verified map of India’s approved ATMP/OSAT projects — who has built what, where, and at what scale — the company map is the reference. The Mohali guide is the hyper-local version for the Punjab corridor, and the supply-chain analysis covers where ISM 2.0’s machines-and-materials incentive applies.
Fidus Synergies advises institutions on building real, plant-linked ATMP/OSAT skilling programmes — the hands-on manufacturing side that India’s new semiconductor facilities need and most colleges don’t yet offer. We publish these resources because the information that should be freely available to students, institutions and partners navigating this space often isn’t — scattered across PIB releases, industry reports and government portals.
Every number in these guides is dated and sourced. Where data conflicts across sources, we note it rather than pick the round number. Where the situation is still developing (NXP in Mohali, SCL’s 25-acre allocation), we flag it explicitly as such.
We advise institutions on real, plant-linked ATMP/OSAT programmes — from model and funding to faculty, certification and placement.
