NITI Aayog Releases India's First 10-Year Semiconductor Roadmap — USD 120–150 Billion Target by 2035
NITI Aayog released India's first 10-year semiconductor roadmap on May 29 — targeting a USD 120–150 billion domestic value chain by 2035, with advanced packaging, compound semiconductors, and design IP as the three pillars.
Finance Minister Nirmala Sitharaman and IT Minister Ashwini Vaishnaw jointly released the roadmap. Three strategic pillars: Advanced OSAT and packaging (chiplets, 2.5D/3D, FOWLP, SiP — targeting top-3 global OSAT position); Compound semiconductors (SiC and GaN for EVs, 5G, defence — where India has genuine materials advantage); and Design IP (100+ advanced design IPs, tiered EDA subsidies, AI-enabled chip design tools). Vaishnaw named design as ISM 2.0's "number one priority."
The roadmap is the first official government document to explicitly state India will not chase leading-edge logic fab below 7nm — a correct call. The strategy is More-than-Moore: packaging, compound materials, and design talent rather than competing with TSMC on process nodes India cannot win.
The roadmap gives institutions a decade-long talent signal. Advanced packaging architects, compound semiconductor process engineers, and EDA-trained chip designers are the three profiles that will be structurally scarce and valuable by 2030. A 6-month OSAT operator programme is the correct starting point — but institutions thinking about Year 3 and beyond need to be building towards chiplets and SiC process training. The institutions that read this roadmap in 2026 and design accordingly will be the ones ISM 2.0 funds in 2027.